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ATmega128
External Memory
Control Register B –
Bit
7
6
5
4
3
2
1
0
XMCRB
Read/ W rite
Initial Value
XMBK
R/ W
0
–
R
0
–
R
0
–
R
0
–
R
0
XMM2
R/ W
0
XMM1
R/ W
0
XMM0
R/ W
0
XMCRB
? Bit 7– XMBK: External Memory Bus-keeper Enable
W riting XMBK to one enables the bus keeper on the AD7:0 lines. W hen the bus keeper is
enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise
be tri-stated. W riting XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so
even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is
one.
? Bit 6..4 – Res: Reserved Bits
These are reserved bits and will always read as zero. W hen writing to this address location,
write these bits to zero for compatibility with future devices.
? Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask
W hen the External Memory is enabled, all Port C pins are default used for the high address byte.
If the full 60 Kbyte address space is not required to access the External Memory, some, or all,
Port C pins can be released for normal Port Pin function as described in Table 5 . As described in
“Using all 64 Kbyte Locations of External Memory” on page 34 , it is possible to use the XMMn
bits to access all 64 Kbyte locations of the External Memory.
Table 5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMM2
0
0
0
0
1
1
1
1
XMM1
0
0
1
1
0
0
1
1
XMM0
0
1
0
1
0
1
0
1
# Bits for External Memory Address
8 (Full 60 Kbyte space)
7
6
5
4
3
2
No Address high bits
Released Port Pins
None
PC7
PC7 - PC6
PC7 - PC5
PC7 - PC4
PC7 - PC3
PC7 - PC2
Full Port C
Using all Locations of
External Memory
Smaller than 64 Kbyte
Since the external memory is mapped after the internal memory as shown in Figure 11 , the
external memory is not addressed when addressing the first 4,352 bytes of data space. It may
appear that the first 4,352 bytes of the external memory are inaccessible (external memory
addresses 0x0000 to 0x10FF). However, when connecting an external memory smaller than 64
Kbyte, for example 32 Kbyte, these locations are easily accessed simply by addressing from
address 0x8000 to 0x90FF. Since the External Memory Address bit A15 is not connected to the
external memory, addresses 0x8000 to 0x90FF will appear as addresses 0x0000 to 0x10FF for
the external memory. Addressing above address 0x90FF is not recommended, since this will
address an external memory location that is already accessed by another (lower) address. To
the Application software, the external 32 Kbyte memory will appear as one linear 32 Kbyte
address space from 0x1100 to 0x90FF. This is illustrated in Figure 17 . Memory configuration B
refers to the ATmega103 compatibility mode, configuration A to the non-compatible mode.
W hen the device is set in ATmega103 compatibility mode, the internal address space is 4,096
bytes. This implies that the first 4,096 bytes of the external memory can be accessed at
32
2467X–AVR–06/11
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